SoC Physical Design Verification Engineer

Tenstorrent
Santa Clara, TX
Category Research
Job Description
Tenstorrent is a leader in AI technology, seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable silicon. The role involves debugging, collaboration, and leading physical verification closure (DRC, LVS, ERC, etc.) for advanced technology nodes. They value collaboration, curiosity, and tackling challenging problems in cutting-edge silicon.

Requirements

  • BS or MS in Engineering (Electrical, Electronics, or related field)
  • 7–14 years of hands-on experience in CPU/IP/SoC physical verification
  • Strong command of industry-standard tools and flows (Calibre, ICV, Pegasus, FC, Innovus, etc.)
  • Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification
  • Solid understanding of advanced node challenges and FinFET design considerations
  • Scripting proficiency (Python, TCL) for automation and flow optimization
  • Familiarity with ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM)

Benefits

  • highly competitive compensation package
  • benefits
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