Staff Logic Design Engineer

Teledyne Technologies Incorporated
Milpitas, CA
Category Engineering
Job Description
We are looking for a top-notch Staff Logic Design engineer to join a dynamic team that develops leading edge test and measurement products. Join our high-speed Protocol Team as a Staff Logic Design Engineer, where you'll architect and implement high-performance digital logic for protocol capture, analysis, and emulation.

Requirements

  • BS in EE, CS or Computer Engineering required
  • MS in EE is a plus
  • 7+ years of experience in digital logic design for FPGA or ASIC
  • Strong proficiency in Verilog/SystemVerilog RTL design
  • Experience with one or more of the following protocols: PCIe, CXL, NVMe, USB, SAS, SATA
  • Experience with Monitoring and/or Test & Measurement tools
  • Experience with PCIe protocol (Gen4/Gen5/Gen6) and familiarity with TLP/DLLP/PHY layer concepts
  • Hands-on with FPGA toolchains (Vivado, Quartus, etc.) and timing closure
  • Knowledge of UVM, assertions, and simulation/debug tools (e.g., ModelSim, Vivado Simulator)
  • Solid understanding of CDC, clock domain design, and reset strategies
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