Analog / SerDes / PLL Design Engineers

Chelsea Search Group
Irvine, CA
Category Engineering
Job Description
I’m searching for a PLL Design Engineer, Analog Design Engineer, and SerDes Design Engineer/Lead for design and verification of analog and mixed-signal circuits in advanced node technologies.

Requirements

  • Master’s degree and/or PhD in Electrical Engineering or related fields
  • 5+ years of experience in analog and mixed-signal circuit design and verification
  • Experience in advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
  • Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling
  • Strong communication and documentation skills
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