Analog / SerDes / PLL Design Engineers

Chelsea Search Group
Irvine, CA
Category Engineering
Job Description
Seeking Analog / SerDes / PLL Design Engineers for Full Time positions in San Diego, CA. Responsibilities include clock generation and distribution, design of custom passive components, and high-speed analog circuit design.

Requirements

  • Master’s degree and/or PhD in Electrical Engineering or related fields
  • 5+ years of experience in advanced CMOS design and verification flows
  • Experience with analog design and verification tools (Virtuoso, Spectre, ADE, and post layout extraction tools)
  • Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other)
  • Good understanding of analog layouts in FinFET and its effect on high-speed designs
  • Knowledge of the fundamentals on electromagnetism, lump models, and high-frequency design
  • Strong communication and documentation skills

Benefits

  • Paid time off
  • Retirement plan
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