Role OverviewDesigns physical silicon layout for high-frequency or high-speed mixed-signal circuits. Creates block-level and chip-top-level floor plans, manages hierarchical block integration, and handles micro-bump or package-aware co-design.
What You Will Do
Addresses layout-dependent effects, device matching, common-centroid structures, guard rings, and isolation or shielding. Ensures complete closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection.
Why It Might Be a Fit
Requires 7+ years of experience in high-speed analog layout design, with a focus on TSMC 4NM and deep sub-micron or advanced CMOS/FinFET nodes.
Requirements
- 7+ years of experience in high-speed analog layout design
- Experience in TSMC 4NM and deep sub-micron or advanced CMOS/FinFET nodes
- Hands-on custom IC layout experience
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