Role OverviewDesigns physical silicon layout for high-frequency or high-speed mixed-signal circuits, creates block-level and chip-top-level floor plans, and manages hierarchical block integration.
What You Will Do
Address layout-dependent effects, device matching, common-centroid structures, guard rings, and isolation or shielding, ensure complete closure on DRC, LVS, ERC, antenna rules, EM/IR reliability, and ESD protection.
Why It Might Be a Fit
Requires 7+ years of experience in high-speed analog layout, TSMC 4NM experience is a must-have, and experience at lower nodes (N3, N5) is critical.
Requirements
- 7+ years of experience in high-speed analog layout
- TSMC 4NM experience
- Experience at lower nodes (N3, N5)
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