Role OverviewDesign and deliver complex, custom ASICs from concept through silicon, collaborating with architecture, verification, physical design, applications, and business teams.
What You Will Do
Lead architectural design, develop detailed specifications, create RTL designs, optimize RTL code, implement and verify complex digital blocks, and collaborate with physical design teams.
Why It Might Be a Fit
Ideal candidate is a high-aptitude engineer with strong, practical experience across the complete ASIC/SoC design lifecycle, and the ability to assume leadership roles and mentor junior engineers.
Requirements
- BSEE/MSEE or equivalent
- 10+ years of direct industry experience with ASIC and/or SoC design
- Proficiency in Synopsys Design Compiler and other EDA tools
- Strong understanding of digital design principles
- Familiarity with RISC architectures (e.g., ARM, MIPS)
- Excellent problem-solving skills and attention to detail
- A strong background in RTL based digital IC design using Verilog/SystemVerilog
- Proven track record of first-pass successes
- A self-starter with the ability to assume leadership roles
- Ability to work well in a diverse team environment
- Willingness to mentor junior engineers
- Experience with industry standard development tools and methodologies
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