Role OverviewThe role requires 8+ years of experience as a Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints. The candidate will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure.
What You Will Do
Responsibilities include overseeing fullchip SDCs, working with physical design and DFT teams to close fullchip timing in multiple timing modes, and developing efficient methodologies to promote block level SDCs to fullchip.
Why It Might Be a Fit
The ideal candidate will have experience with block/full chip SDC development, Static Timing Analysis, and prior working experience with STA tools like PrimeTime/Tempus. They will also have a strong understanding of related digital design concepts and experience with synthesis tools, Verilog/System Verilog programming, and scripting languages.
Requirements
- 8+ years of experience in ASIC or related field
- Bachelor’s Degree in Electrical or Computer Engineering
- Experience with block/full chip SDC development in functional and test modes
- Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
- Understanding of related digital design concepts (e.g. clocking and async boundaries)
- Experience with synthesis tools (e.g. Synopsys DC/DCG/FC), Verilog/System Verilog programming
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