Role OverviewThe role requires a diligent Design/SDC Engineer with strong analytical skills to work on timing constraints, clock groups, and clock exclusivity. The candidate will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure.
What You Will Do
Responsibilities include overseeing fullchip SDCs, working with physical design and DFT teams to close fullchip timing in multiple timing modes, and developing efficient methodology to promote block level SDCs to fullchip.
Why It Might Be a Fit
The candidate will contribute to developing next-generation networking chips, review block level SDCs and clocking diagrams, and mentor other RTL design owners on SDC development.
Requirements
- Bachelor’s Degree in Electrical or Computer Engineering
- 7+ years of ASIC or related experience
- Experience with block/full chip SDC development in functional and test modes
- Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
- Understanding of related digital design concepts (eg. clocking and async boundaries)
- Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming
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