ASIC Design Verification Lead

Requirements

• Define and own block-, subsystem-, and chip-level verification strategies
• Develop and maintain scalable verification environments using SystemVerilog and UVM
• Drive execution from test-plan definition through coverage and bug closure
• Ensure verification readiness as a gating requirement for tape-out
• Write and review high-quality testbenches, sequences, checkers, and scoreboards
• Develop constrained-random, directed, and stress tests to validate complex corner cases
• Actively debug functional failures across RTL, testbench, and simulation environments
• Define functional, code, and assertion coverage goals
• Analyze coverage results and identify verification gaps
• Provide clear, actionable feedback to RTL designers to improve design and test quality
• Partner closely with RTL, architecture, physical design, and firmware teams
• Drive root-cause analysis of functional, performance, and integration issues
• Support gate-level, timing-aware, and power-aware simulations as required
• Partner and support emulation and post silicon validation of the ASIC design
• Lead full-chip verification planning, execution, and closure
• Support emulation and acceleration environments where appropriate
• Ensure clean handoff to silicon bring-up teams with high confidence in design correctness
• Establish and enforce verification checklists and quality gates
• Track verification progress and risk, proactively escalating issues
• Lead by technical authority and hands-on contribution rather than coordination alone
• Continuously improve verification methodology, infrastructure, and best practices

Benefits

• Competitive salary
• Opportunity to shape the future of AI infrastructure
• Work with a world-class team on groundbreaking technology
• Transform data center capabilities