ASIC RTL/SoC Design Engineer

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs. Collaborate with cross-functional teams to achieve cohesive and successful product development and delivery.

What You Will Do

Design, simulate, and verify ASIC/SoC products, integrate and validate IP blocks, conduct PPA analysis, and provide crucial support for Post-Si testing and validation.

Why It Might Be a Fit

The ideal candidate will have experience with Verilog and system Verilog, VCS, Verdi, and other industry standard tools, and a strong understanding of the design flow. Familiarity with AMBA APB AXI Protocol, RISC/Arm or other core architectures, and ability to create innovative architecture and solutions to customer requirements.

Requirements

• MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
• Experience with Verilog and system Verilog
• Experience with VCS, Verdi or other industry standard tools
• Experience with pre-layout simulation and post-layout simulation
• Understanding of the design flow. Ability to work with the backend team
• Familiarity with AMBA APB AXI Protocol
• Familiarity with RISC/Arm or other core architectures
• Ability to create innovative architecture and solutions to customer requirements

Benefits

• Competitive salary range: $110,000 - $300,000 / year
• Equal Opportunity Employer
• Inclusive environment for all employees
• Reasonable accommodations for qualified applicants with disabilities