ASIC Technical Lead - DFT

The ASIC Technical Lead - DFT will be responsible for implementing Hardware Design-for-Test (DFT) features, developing innovative DFT IP, and working closely with design and physical design teams to enable integration and validation of test logic.

What You Will Do

Responsible for implementing DFT features, developing DFT IP, and working with design and physical design teams to integrate and validate test logic.

Why It Might Be a Fit

The ideal candidate will have experience with Jtag protocols, Scan and BIST architectures, and EDA tools like TestMax, Tetramax, and Tessent tool sets.

Requirements

• Bachelor's or Master's Degree in Electrical or Computer Engineering
• At least 10 years of experience
• Experience with Jtag protocols, Scan and BIST architectures
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets
• Prior verification experience including System Verilog Logic Equivalency checking

Benefits

• Medical, dental and vision insurance
• 401(k) plan with Cisco matching contribution
• Paid parental leave
• Short and long-term disability coverage
• Basic life insurance
• Paid time away (10 paid holidays, 1 floating holiday, 1 paid day off for birthday, paid year-end holiday shutdown, 4 paid days off for personal wellness)
• 16 days of paid vacation time per full calendar year
• 80 hours of sick time off provided on hire date and each January 1st thereafter
• Optional 10 paid days per full calendar year to volunteer
• Annual bonuses subject to Cisco's policies
• Performance-based incentive pay on top of base salary for sales roles