Design Verification Engineer

We are seeking a Design Verification Engineer with experience in developing and maintaining UVM/SystemVerilog testbenches for high-performance IPs. The ideal candidate will have expertise in SV/UVM, PCIe/Ethernet/HBM, and experience working on Amazon tools, flows, and methodology.

What You Will Do

Developing and maintaining UVM/SystemVerilog testbenches, regression/triage, and coverage closure. The candidate will also need to work on Amazon tools, flows, and methodology.

Why It Might Be a Fit

The ideal candidate will have strong skills in SV/UVM, AXI expertise, NOC/Crossbar, and performance. They will also need to be able to work effectively in a start-up mode with less documentation available.

Requirements

• 8 to 15 years of experience in ASIC or a related field
• Bachelor's degree in electrical or computer engineering
• Master's Degree in Electrical or Computer Engineering with at least 8 years of experience in ASIC or a related discipline