Digital Design Verification Engineer

Flux
San Francisco, CA
Job Description
We are seeking highly skilled and motivated Senior/Staff Digital Verification Engineers to take ownership of the functional correctness of high-speed, real-time data-processing silicon. The ideal candidate brings deep expertise in digital verification methodologies, a solid understanding of hardware architecture, and a passion for building provably correct, high-performance systems that underpin breakthrough AI hardware.

Requirements

  • 5+ years of hands-on experience in digital verification for high-performance ASICs or SoCs
  • Ownership of verification for at least one complex block or subsystem processing continuous real-time data streams
  • Strong proficiency in SystemVerilog, assertions (SVA), and modern verification methodologies (e.g. UVM, CocoTB)
  • Proven experience verifying designs operating in GHz-class clock domains, including CDC/RDC analysis
  • Familiarity with industry-standard EDA flows: RTL simulation, formal verification, linting, CDC/RDC, STA, power-intent (UPF/CPF), and gate-level simulation
  • Experience verifying high-speed IP such as SerDes, DDR/HBM, PCIe, Ethernet, or similar interfaces
  • Proficiency with MATLAB/Simulink or Python/NumPy for algorithm modelling, fixed-point analysis, and test-vector generation
  • Solid grounding in digital design principles, computer architecture, DSP fundamentals, and semiconductor basics
  • Clear communicator who collaborates effectively across disciplines and is comfortable operating in a fast-moving, evolving environment

Benefits

  • Competitive salary and stock options
  • Financial and operational relocation support (US and abroad)
  • 401(k) retirement savings plan with employer match (commonly in the 4-5% range)
  • Top of the line, high-spec tech for everyone
  • Personal company card to spend on tools that help you do your job
  • Periodic travel to London HQ and regular team socials
  • 33 days of paid time off (PTO), including US federal holidays
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