Digital Verification Engineer

Requirements

• Develop and maintain simulation-based verification environments for SystemVerilog RTL (UVM and/or cocotb-based flows).
• Create scalable testbenches, drivers/monitors, scoreboards, reference models, and coverage (functional/code) to validate IP and SoC behavior.
• Build and execute constrained-random and directed tests; debug failures across RTL, testbench, and tool flows.
• Define verification plans, coverage goals, and bring-up strategies in collaboration with design and architecture.
• Drive regressions and continuous integration for verification, including test triage, automation, and reporting.
• Contribute to verification best practices (assertions, checkers, reuse, documentation) across the Core Platform.