High-Speed CMOS DAC/ADC/PLL Analog Design Engineer

Requirements

• BSEE with 10+ years or MSEE with 7+ years or PhDEE with 5+ years of High-Speed CMOS DAC/ADC/PLL Analog Design experience
• Experience in advance cmos design and verification flows (tools to evaluate self-heating, electromigration, safe operating area)
• Experience in advanced CMOS/FinFET technologies (TSMC process nodes N3, N5, N7) and optimization for high performance circuits
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
• Experience with electromagnetic simulation tools (EMX, Momentum, HFSS or other) is a plus
• Experienced in lab chip bring-up and debugging efforts is a plus
• Good understanding of analog layouts in FinFET and its effect on high-speed designs is a plus
• Knowledge of the fundamentals on electromagnetism, lump models and high-frequency design
• Production level tape out experience
• Strong communication and documentation skills