High-Speed CMOS DAC/ADC/PLL Analog Design Engineer

Chelsea Search Group

Irvine, TX

Category Engineering

Job Description

High-Speed CMOS DAC/ADC/PLL Analog Design Engineer position available for a fast-growing startup company.

Requirements

BSEE with 10+ years or MSEE with 7+ years or PhDEE with 5+ years of High-Speed CMOS DAC/ADC/PLL Analog Design experience
Experience in advance CMOS design and verification flows (tools to evaluate self-heating, electromigration, safe operating area)
Experience in advanced CMOS/FinFET technologies (TSMC process nodes N3, N5, N7) and optimization for high performance circuits
Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools)
Good understanding of analog layouts in FinFET and its effect on high-speed designs
Knowledge of the fundamentals on electromagnetism, lump models and high-frequency design
Production level tape out experience
Strong communication and documentation skills

]]>