Role OverviewThe Lead ASIC Design Verification Engineer will establish, staff, and lead the ASIC verification team, architecting and building UVM testbenches, defining verification methodology, and owning verification schedule and risk.
What You Will Do
You will personally architect and build UVM testbenches, define verification methodology, own verification planning, and serve as the verification voice in design and architecture reviews.
Why It Might Be a Fit
This role is for a strong verification engineer who wants to build their own team and lead the verification effort.
Requirements
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 8+ years of ASIC/SoC verification experience
- Expert-level SystemVerilog and UVM
- Strong command of constrained-random verification, functional coverage, coverage-driven closure, and assertion-based verification with SVA
- Experience with commercial simulation and coverage tools (Synopsys VCS/Verdi, Cadence Xcelium, and/or Siemens Questa)
- Working knowledge of digital design and RTL
- Scripting proficiency for verification infrastructure (Python, Perl, TCL, and shell)
- Demonstrated technical leadership
- Clear written and verbal communication
- U.S. Citizenship and ability to obtain and maintain a U.S. Government security clearance
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