Role OverviewA Lead ASIC Design Verification Engineer will establish, staff, and lead our ASIC verification team. This is a hands-on technical leadership role – you will personally architect and build UVM testbenches for our current programs while simultaneously defining the verification methodology, infrastructure, and hiring plan that will scale the function from a single contributor to a full team.
What You Will Do
You will be the technical authority on verification – setting coverage-driven sign-off criteria, owning verification schedule and risk for tapeouts, and making the build-versus-buy calls on VIP, tools, and compute.
Why It Might Be a Fit
If you have been the strongest verification engineer on someone else’s team and want to build your own, this is the role.
Requirements
- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 8+ years of ASIC/SoC verification experience
- Expert-level SystemVerilog and UVM
- Strong command of constrained-random verification, functional coverage, coverage-driven closure, and assertion-based verification with SVA
- Experience with commercial simulation and coverage tools (Synopsys VCS/Verdi, Cadence Xcelium, and/or Siemens Questa) and with regression management at scale
- Working knowledge of digital design and RTL
- Scripting proficiency for verification infrastructure (Python, Perl, TCL, and shell) and fluency with Git-based workflows and Linux development environments
- Demonstrated technical leadership: mentoring engineers, leading a verification effort, or owning verification schedule and sign-off for a program
- Clear written and verbal communication – including the ability to present verification status and evidence to non-verification stakeholders and customers
- U.S. Citizenship is required due to ITAR and DFARS requirements applicable to our programs, along with the ability to obtain and maintain a U.S. Government security clearance
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