Mixed Signal Verification Engineer

5 Star Recruitment
Austin, TX
Category Engineering
Job Description
We are seeking a Mixed Signal Verification Engineer with 5+ years of experience in Behavioural Modelling (BM) of Analog design for digital verification. The ideal candidate will have experience in Verilog/SystemVerilog coding, Virtuoso Schematics tools, and UVM.

Requirements

  • 5+ years of total experience
  • Experience in Behavioural Modelling (BM) of Analog design for digital verification
  • Experience in Verilog/SystemVerilog coding
  • Experience in Virtuoso Schematics tools
  • Experience in UVM
  • Verification Methodologies and Tools: Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection.
  • Collaborative Environment: Ability to verify Analog/mixed-signal designs in a collaborative team environment.

Benefits

  • Will sponsor H1-B
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