MTS DRAM High Speed Interface Design Architect, HBM

Micron Technology
Boise, TX
Category Research
Job Description
Micron Technology is seeking a DRAM High Speed Interface Design Architect for HBM cube, responsible for designing and developing interfaces, including DRAM command and control logic, serializing/de-serializing schemes. The role involves collaboration with a development team and applying memory technologies to build groundbreaking HBM products. Successful candidates will contribute to the design, layout, and optimization of memory, logic, and analog circuits.

Requirements

  • Extensive experience with DRAM operation and JEDEC specifications, preferably with DDR/LPDDR/GDDR/HBM product family
  • In-depth technical expertise in analog and mixed-signal design
  • Hands-on experience in DRAM Command decoding, bank logic, and RAS/CAS chain design is highly desired
  • Proven track record of innovation and problem-solving in high-performance memory development
  • Excellent problem-solving and analytical skills
  • An initiative-taking, hardworking collaborator who enjoys working with others
  • Excellent communication skills
  • Minimum 10+ years of proven experience in the Memory industry with an MS degree or 15+ years with a BS degree or equivalent experience

Benefits

  • Medical, dental, and vision plans
  • Beneficial programs for illness and injury
  • Paid family leave
  • Paid time-off program
  • Paid holidays
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