Role OverviewJoin our dynamic Test Chip Physical Implementation team in San Jose, CA, and play a critical role in bringing TSMC’s most advanced process nodes (A16/A14/A10) to life. This is an exciting opportunity for an engineer with a strong foundation in VLSI design, a passion for innovation, and hands-on experience with cutting-edge EDA tools.
What You Will Do
Drive the end-to-end physical implementation and tapeout of test vehicles on TSMC’s leading-edge process nodes (A16/A14/A10). Execute comprehensive physical design flows from netlist-to-GDS, including block and SoC-level floorplanning, power grid implementation, and low-power structure integration.
Why It Might Be a Fit
Actively contribute to the development and evaluation of advanced methodologies and flows to meet aggressive PPA goals. Collaborate effectively with cross-functional teams, including RTL, DFT, and CAD, to provide insightful feedback and ensure seamless integration throughout the design cycle.
Requirements
- Master’s Degree or higher in Electrical Engineering or Computer Science
- A minimum of 3 years of industrial experience in physical design or a closely related field within the semiconductor industry
- Demonstrated expertise in digital circuit concepts and a deep understanding of the full physical design implementation flow
- Hands-on experience with major EDA tools from Synopsys and Cadence
- Proficiency in scripting languages such as Python, TCL, CSH, Verilog, and Unix shell scripting
- Strong analytical and problem-solving skills with meticulous attention to detail
- Excellent written and verbal communication skills
Benefits
- Market competitive pay
- Allowances
- Bonuses
- Comprehensive benefits
- Extensive development opportunities and programs
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