Principal Digital Design Engineer

Renesas Electronics
Any Location, GA
Category Engineering
Job Description
Renesas is seeking a Principal Digital Design Engineer to develop digital sections of leading-edge memory data buffer chips for DDR5, DDR6, and beyond. The role involves proposing, architecting, and designing RTL in Verilog, contributing to a highly experienced team, and mentoring junior engineers.

Requirements

  • Bachelor or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
  • Minimum 12+ years of experience
  • 8+ years of direct experience in ASIC/IC design
  • Experience in architecting digital designs and writing device-level or sub-system specifications
  • Fluent in Verilog RTL coding and ASIC design methodology
  • Expertise in digital design implementation, including logical synthesis and DFT insertion with high coverage
  • Experience with static timing analysis and creation of place and route constraints
  • Proficiency in formal verification, linting, and CDC/RDC checking
  • Knowledge of asynchronous clock crossings and synthesis implications of RTL
  • Experience implementing and verifying ECOs on RTL, synthesized, and post-route netlists
  • Competence in developing design constraints for synthesis, STA, and P&R hand-off
  • Experience with gate-level simulations and understanding the causes and implications of timing violations
  • Familiarity with ATPG generation and ATE support (a plus)
  • Experience in DFT or physical design (a plus)

Benefits

  • Comprehensive health insurance
  • 401(k) Matching
  • Generous Paid Time Off
  • Relocation Assistance
  • Remote work option
  • Employee Resource Groups
  • Flexible and inclusive work environment
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