Role OverviewAs a Principal Physical Design Engineer, you will serve as a foundational pillar in translating complex architectural concepts into high-yield, production-ready silicon. Operating at the cutting edge of semiconductor design, you will spearhead end-to-end netlist-to-GDSII implementation for ultra-large-scale, high-performance computing (HPC) and AI silicon architectures.
What You Will Do
Drive full-flow RTL/Netlist-to-GDSII physical implementation, taking high-complexity, multi-million gate blocks through synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and final signoff.
Why It Might Be a Fit
We are seeking a seasoned, intellectually curious individual who thrives on engineering rigor and structural precision. This position follows a high-impact, hybrid collaboration model (4 days on-site) designed to accelerate tight engineering feedback loops and direct technical partnership.
Requirements
- Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, Microelectronics, or a closely related technical field.
- 10+ years of direct, hands-on experience in full-chip or block-level physical design implementation and signoff with a proven track record of successful tapeouts.
- Demonstrated mastery of industry-standard EDA tool suites (e.g., Synopsys Fusion Compiler/ICC2, PrimeTime, StarRC; Cadence Innovus, Tempus, Voltus; Siemens Calibre).
- Proven track record implementing designs in TSMC N16/N12 or below, with deep knowledge of advanced FinFET parasitic extraction, multi-patterning, and variability effects.
- Proficient scripting ability in Tcl, Perl, and/or Python to construct, maintain, and debug complex automation pipelines and signoff scripts.
Benefits
- Comprehensive benefits package
]]>