Principal Firmware/Middleware Engineer

As the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. You will bridge the gap between cutting-edge silicon (ASICs) and upper-layer cluster orchestration software. You will define how firmware manages complex scale-up topologies, ensures raw hardware performance (maximizing bandwidth and minimizing latency), and maintains absolute reliability across thousands of connected AI accelerators.

What You Will Do

You will be responsible for architectural definition & design, initialization, boot, & fabric management, performance, RAS, & security. You will design deterministic, fast link-training state machines to bring up ultra-high-speed die-to-die and chassis-to-chassis UALink connections, architect efficient algorithms for runtime topology discovery, dynamic routing, and credit management to prevent fabric congestion, and lead the design of SDKs and APIs that expose switch functionality to baseboard management controllers (BMCs) using OpenBMC and Redfish APIs.

Why It Might Be a Fit

You will have the opportunity to work on world-leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future. Renesas is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination.

Requirements

• Bachelor’s or Master’s/Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline.
• 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development.
• Expert-level proficiency in C for bare-metal and RTOS environments (e.g., ThreadX, FreeRTOS, Zephyr) and Python for hardware automation and modeling.
• Deep technical understanding of high-speed scale-up/scale-out interconnect protocols (UALink, NVLink, CXL, or PCIe Gen5/Gen6).
• Comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management.
• Strong familiarity with hardware debuggers (JTAG, Lauterbach Lauterbach/TRACE32) and lab equipment (Oscilloscopes, PCIe/Protocol Analyzers).

Benefits

• Competitive benefits package
• Equal opportunity and affirmative action employer
• Supporting diversity and fostering a work environment free of discrimination