Principal Firmware/Middleware Engineer

As the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for our next-generation AI cluster scale-up switches. You will bridge the gap between cutting-edge silicon (ASICs) and upper-layer cluster orchestration software. You will define how firmware manages complex scale-up topologies, ensures raw hardware performance (maximizing bandwidth and minimizing latency), and maintains absolute reliability across thousands of connected AI accelerators.

What You Will Do

Your responsibilities will include architectural definition and design, initialization, boot, and fabric management, performance, RAS, and security. You will fine-tune bare-metal execution paths to guarantee deterministic low latency for collective communication primitives, design robust error-handling, telemetry, and fault-isolation micro-architectures, and implement secure boot, cryptographic firmware authentication, and runtime attestation to ensure fabric integrity.

Why It Might Be a Fit

To be successful in this role, you will need to have 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development. You will require expert-level proficiency in C for bare-metal and RTOS environments and Python for hardware automation and modeling. You will also need to have a deep technical understanding of high-speed scale-up/scale-out interconnect protocols and comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management.

Requirements

• Bachelor’s or Master’s/Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline
• 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development
• Expert-level proficiency in C for bare-metal and RTOS environments (e.g., ThreadX, FreeRTOS, Zephyr) and Python for hardware automation and modeling
• Deep technical understanding of high-speed scale-up/scale-out interconnect protocols (UALink, NVLink, CXL, or PCIe Gen5/Gen6)
• Comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management

Benefits

• Competitive salary
• Bonus opportunities
• Healthcare
• PTO
• Retirement
• Learning budget
• Parental leave
• Wellness
• Visa/relocation
• Remote flexibility
• Stipends