Principal High-Speed Analog Layout Engineer

Requirements

• Minimum 5+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
• At least 1 year of experience with TSMC FinFET process nodes (3nm N3, 5nm N5, 7nm N7, or 16nm N16)
• Deep understanding of device physics, layout-dependent effects, and their impact on circuit performance
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
• Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
• Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
• Experience working in collaborative environments with international and remote teams
• Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
• Experience using revision control systems for layout design management

Benefits

• Full-time Employee
• Bonus
• Benefits
• 401k
• Stock Options