Principal Physical Verification Engineer

Requirements

• Lead full chip Physical Verification effort
• Own execution plans, schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness.
• Conduct full chip and blocks PV checks
• Work with internal analog team to ensure clean IP delivery
• Responsible for running and analyzing DRC/ERC/LUP/PERC results
• Experience with using either ICV or Calibre verification tools
• Understanding advance TSMC DRC rules
• Partner with analog, block, chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy.
• Participate in tapeout readiness reviews.