Principal Verification Engineer I

CesiumAstro
Austin, TX
Job Description
CesiumAstro is seeking a Principal Verification Engineer I to lead the evaluation and technical implementation of FPGA and digital design simulation, verification and emulation infrastructure. The successful candidate will have expertise in FPGA digital design verification techniques, including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP.

Requirements

  • Bachelor of Science (BS) or Master of Science (MS) degree in Computer Science, Electrical Engineering, or Computer Engineering or related engineering discipline.
  • Minimum of 9 years of industry experience in verification and automation.
  • Expert-level knowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP.
  • Expert-level knowledge of digital design automation infrastructure, including CI, regression testing and HIL testing.
  • Advanced-level knowledge of Linux.
  • Advanced-level knowledge of vendor-provided FPGA development tools with a focus on Xilinx tools.
  • Desire and ability to train and mentor while maintaining a positive and productive attitude.
  • A deep sense of ownership of your work, and for the success of the company.

Benefits

  • Company stock options
  • Health insurance
  • Dental insurance
  • Vision insurance
  • HSA
  • FSA
  • Life insurance
  • Disability insurance
  • Retirement plans
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