Principal Verification Engineer I

Requirements

• Lead the evaluation and technical implementation of FPGA and digital design simulation, verification and emulation infrastructure
• Lead the development, maintenance and phased deployment of continuous integration and regression testing infrastructure
• Develop state-of-the-art UVMf-based top-level and module-level testbenches using block-to-top best practices for reusability
• Lead the development of reusable custom VIP modules
• Work closely with the engineering and senior leadership teams to train and mentor engineers at all experience levels on UVMf testbench usage and modern approaches to FPGA/digital design

Benefits

• Generous benefits package including health, dental, vision, HSA, FSA, life, disability and retirement plans
• Company stock options