Role OverviewThe role requires a Design Engineer with strong experience in Timing Constraints Writing, specifically in the RTL to Physical Design (RTL2PD) stage. The candidate will be working on RTL Synthesis, Constraint writing, validation, and Static timing Analysis.
What You Will Do
The candidate will be responsible for RTL Synthesis, Constraint writing, validation, and Static timing Analysis, as well as writing scripts and modifying scripts for RTL synthesis, SDC creation, and STA. They will also be debugging synthesis issues and STA, and generating clean netlists.
Why It Might Be a Fit
The ideal candidate will have 8-12 years of hands-on experience in RTL Synthesis, EDA exposure, and experience working with multi-node designs.
Requirements
- 8-12 years of hands-on RTL Synthesis experience
- Experience with EDA tools such as Design Compiler, PrimeTime, Tempus, and Genus
- Experience working with multi-node designs (16nm, 7nm, etc.)
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