Role OverviewThe Samsung Research America SOC Architecture Lab is looking for a SOC Architect Fabric, System Cache and DRAM Controller to help architect next generation SOCs. This is a highly visible hands-on role leading individual and team contributions to Fabric, System cache and DRAM controller sub-system architecture, interface, performance and power tradeoffs.
What You Will Do
Guide on development of innovative Fabric, System cache and DRAM controller Architectural and microarchitectural features to boost power and performance on various targeted workloads in next generation SOCs. Identify and deliver Fabric, System cache and DRAM controller subsystem architecture proposals for products in new and existing markets.
Why It Might Be a Fit
Prior direct experience (> 7 years) in Fabric, System Cache, DRAM controller Architecture or microarchitecture is required. Understanding of memory controller architecture, memory scheduling, prioritization and QoS is also necessary.
Requirements
- BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
- 3+ years of experience in SOC or ASIC design and architecture
- Prior direct experience (> 7 years) in Fabric, System Cache, DRAM controller Architecture or microarchitecture
- Understanding of memory controller architecture, memory scheduling, prioritization and QoS
- Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB)
- Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM, and the ability to analyze such standards and drive recommendations
- Background in memory systems and computer architecture to understand the tradeoffs among memory bandwidth, latency, performance, power, SoC area
Benefits
- Annual bonus eligibility
- Generous benefits
- Base pay range: $158,800—$218,100 USD
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