Senior High-Speed Analog Layout Engineer

Chelsea Search Group
San Jose, CA
Category Data Analyst
Job Description
Senior High-Speed Analog Layout Engineer responsible for leading and owning the physical layout design of complex analog/mixed-signal macros, collaborating with schematic designers, and mentoring junior engineers. Required experience with advanced CMOS/FinFET technologies, TSMC FinFET process nodes, and layout best practices. Familiarity with Cadence Virtuoso, Calibre, and other layout and verification tools. Preferred experience with optical or high-speed analog interfaces, layout automation, and revision control systems.

Requirements

  • Minimum 5+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies
  • Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred)
  • At least 1 year of experience with TSMC FinFET process nodes (3nm N3, 5nm N5, 7nm N7, or 16nm N16)
  • Deep understanding of device physics, layout-dependent effects, and their impact on circuit performance
  • Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
  • Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
  • Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
  • Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
  • Experience working in collaborative environments with international and remote teams
  • Strong documentation and communication skills with the ability to clearly present layout trade-offs and status to cross-functional teams
  • Experience using revision control systems for layout design management

Benefits

  • Full-time Employee
  • Bonus
  • Benefits
  • 401k
  • Stock Options
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