Role OverviewThis role is responsible for architecting, designing, and delivering memory layout solutions within hardware and embedded systems projects. The individual serves as a subject matter expert, driving technical excellence and innovation by leveraging advanced memory mapping strategies and tools.
What You Will Do
Key responsibilities include architecting and designing advanced memory layouts, leading solution development for product and sustenance projects, and providing subject matter expertise in memory mapping, address decoding, and timing closure.
Why It Might Be a Fit
The ideal candidate will have expert proficiency in memory layout design using EDA tools, excellent understanding of memory organization principles, and advanced skills in memory mapping, address decoding, and timing closure techniques.
Requirements
- Expert proficiency in memory layout design using Synopsys, Cadence, or Mentor Graphics EDA tools
- Excellent understanding of memory organization principles for SRAM, DRAM, Flash, and non-volatile memories
- Advanced skills in memory mapping, address decoding, and timing closure techniques
- Solid capability in schematic capture, layout editing, and physical verification for memory blocks
- Strong knowledge of low-power memory design and reliability optimization
- Experience with memory verification flows, DRC/LVS checks, and post-layout simulation
Benefits
- Medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance
- Employee assistance program
- 401(k) retirement plan
- 10 days of paid time off per year
- 10 paid holidays per year
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