Role OverviewAs a Senior Physical Design Engineer, you will be responsible for the physical design implementation PnR run, Performance/Power/Area (PPA) comparison, congestion & DRC analysis, and design optimization. You will be reporting to Manager of Advanced Chip implementation team at its San Jose Design Center, California and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company.
What You Will Do
Responsible for the physical implementation on TSMC’s most advanced process nodes. Netlist-to-GDS flow including block/soc-level placement, clock tree synthesis, routing, and design optimization.
Why It Might Be a Fit
In depth knowledge of hardware design courses including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation. Experience in research projects or internship related to RTL coding, synthesis, digital design and testing, physical implementation or design verification.
Requirements
- Master’s degree in Electrical Engineering or Computer Science
- Minimum of 4 years of relevant industry experience
- In depth knowledge of hardware design courses
- Experience in research projects or internship related to RTL coding, synthesis, digital design and testing, physical implementation or design verification
- In depth knowledge of major EDA tools/design flows
- Experience in Python/Perl/TCL language programming and CSH script
Benefits
- Market competitive pay
- Allowances
- Bonuses
- Comprehensive benefits
- Extensive development opportunities and programs
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