Role OverviewWe are seeking an experienced Physical Design / P&R Engineer to take a key role in delivering complex, high-performance ASICs from RTL/netlist through GDSII and tapeout.
What You Will Do
You’ll own critical aspects of physical implementation, including floorplanning, placement, CTS, routing, timing closure, and PPA optimization, working with advanced technologies such as RISC-V, DDR, and SerDes.
Why It Might Be a Fit
This is an opportunity to make a significant technical impact while collaborating with a highly experienced, multidisciplinary ASIC engineering team.
Requirements
- 10+ years of direct industry experience with ASIC and/or SoC design
- BSEE/MSEE or equivalent
- Excellent problem-solving skills and attention to detail
- Experience with industry standard development tools and methodologies
- Familiarity with RISC architectures (e.g., ARM, MIPS)
- Proficiency in Synopsys Design Compiler and other EDA tools
- Proven track record of first-pass successes
- Self-starter with the ability to assume leadership roles
- Strong background in RTL based digital IC design using Verilog/SystemVerilog
- Strong understanding of digital design principles
- Willingness to mentor and develop less experienced engineers
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