Senior Principal Program Manager, ASIC Post-Silicon Engineering

Astera Labs is seeking a Senior Principal Post-Silicon Technical Program Manager to lead execution of complex post-silicon programs for AI connectivity products. This role owns cross-functional program delivery from silicon power-on through bring-up, validation, qualification, customer sampling, and release to manufacturing - RTM, aligning engineering execution with product, customer, and business milestones.

What You Will Do

Own the integrated post-silicon program plan from silicon power-on through bring-up, validation, qualification, customer sampling, and RTM, ensuring alignment across silicon, firmware/software, platform, compliance, production test and manufacturing milestones. Drive program schedules, budgets, resources, interdependencies, and risk management, balancing scope, schedule, and cost trade-offs while maintaining clear communication with executives and key stakeholders.

Why It Might Be a Fit

The ideal candidate brings deep experience leading technically complex semiconductor or systems programs involving silicon, firmware, software, platform, validation, manufacturing, and customer readiness. They are highly effective at driving cross-functional alignment, managing program risk, and communicating crisply with both engineering teams and executive stakeholders.

Requirements

• 10+ years of experience in semiconductor engineering, post-silicon validation, system validation, silicon bring-up, product engineering, product applications, FAE, or technical program management with a strong technical background.
• Strong experience leading post-silicon execution for complex ASIC, SoC, FPGA, SerDes, Ethernet, PCIe, CXL, networking, AI infrastructure, cloud, data center, or high-performance compute products.
• Demonstrated ability to manage products from first silicon through validation, customer sampling, qualification, RTM, and manufacturing readiness.
• Deep understanding of silicon validation flows, including bring-up, debug, characterization, interoperability, compliance, regression execution and issue triage.
• Experience managing FW development cycle, experience with JIRA, Confluence, dashboards, issue-tracking systems.
• Experience working with cross-functional teams across architecture, silicon design, firmware, software, electrical validation, system validation, product engineering, test, manufacturing, quality, operations, applications engineering, and customer-facing organizations.
• Strong technical knowledge in one or more of the following: High-speed SerDes, Ethernet, PCIe, CXL, NVMe, or similar protocols, AI server, networking, or data center platforms, Signal integrity, eye diagrams, jitter, noise, impedance, and link training, FEC, protocol compliance, and interoperability validation, Firmware/hardware/software interaction, Board, platform, and system-level debug, Electrical validation and lab-based debug, Optical or Active electrical modules.

Benefits

• Discretionary bonus
• Incentives
• Benefits