Role OverviewWe are seeking a Senior Silicon Physical Design and Layout Engineer to design and develop advanced integrated circuits for our revolutionary space-based communications network. The ideal candidate brings expertise in physical design methodologies, layout techniques, and semiconductor technologies, thriving in a fast-paced environment where innovation meets mission-critical execution.
What You Will Do
Execute physical design and layout of ASICs that integrate both analog and digital processing, implement floor planning, power distribution, clock tree synthesis, and routing for complex mixed-signal designs, and optimize layouts for radiation tolerance and reliability in the space environment.
Why It Might Be a Fit
The ideal candidate will have 7+ years of experience in physical design and layout of ASICs, demonstrated expertise in digital and analog layout techniques, and experience with industry-standard EDA tools for physical design (Cadence, Synopsys, or Mentor).
Requirements
- B.S. degree in Electrical Engineering, Computer Engineering, or related field
- 7+ years of experience in physical design and layout of ASICs
- Demonstrated expertise in digital and analog layout techniques
- Experience with industry-standard EDA tools for physical design (Cadence, Synopsys, or Mentor)
- Knowledge of semiconductor fabrication processes and design rules
- Understanding of timing closure and signal integrity challenges
- Experience with power analysis and optimization techniques
Benefits
- Medical
- dental
- vision
- basic and supplemental life insurance
- paid parental leave
- short and long-term disability
- 401(k) with a company match of up to 5%
- Education Support Program
- Stock Options for all regular employees (working at least 20 hours/week)
- Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays
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