Senior SoC Design Verification Engineer (remote)

Requirements

• 7+ years of hands-on experience in SoC verification using UVM
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
• Experience in Gate-Level Simulation (GLS) setup and process corner failure analysis
• Experience using Cadence verification tools such as VCS, Verdi, and Spyglass
• Experience writing and debugging RTL using SystemVerilog
• Familiarity with digital design concepts and ASIC development flow
• Programming experience using C, C++, and/or Python/Perl
• Ability to multi-task and prioritize in a fast-paced environment
• Ability to work collaboratively across teams and communicate effectively
• Attention to detail and remarkable eye for accuracy
• Strong analytical and problem-solving skills
• Willingness to learn and develop new skills

Benefits

• Full-time/employee + Bonus, Benefits, 401k, Stock Options