Senior SoC Design Verification Engineer (remote)

Requirements

• BSEE/MSEE with 15+ years of hands-on experience in SoC verification using UVM
• Experience in Gate Level Simulation (GLS) setup and process corner failure analysis
• Experience using Cadence verification tools such as Xcelium, SimVision, and JasperGold
• Experience writing and debugging RTL using SystemVerilog
• Programming experience using C, C++, and/or Python/Perl
• Familiarity with digital design concepts and ASIC development flow

Benefits

• Competitive salary
• Bonus
• Stock
• Employer-paid health care
• Flexible time off
• Flexible work location with remote options
• 401K employer match