Senior SoC RTL Design Engineer (remote)

Requirements

• BSEE/MSEE with 10+ years of SoC design/architecture experience
• Asynchronous logic design experience
• Clock domain crossing methodologies
• Experience with RISC-V architecture
• Logic synthesis and static timing analysis
• Modeling SoC architectures with FPGAs
• RTL Design including HVLs and HDLs (SystemVerilog, Verilog)
• Scripting languages such as Python, Perl, Tcl, shell, etc.
• SoC design flow including chip-level design, block/IP design and behavioral modeling
• Strong familiarity with EDA tools
• Strong problem solving and debugging capabilities
• Third Party IP Integration experience
• Working knowledge of PCIe and DDR
• Working knowledge of SoC design with CHISEL (plus)
• Working knowledge of standard bus protocols such as AXI/AMBA/TileLink (plus)

Benefits

• Full-time/employee + Bonus
• Benefits
• 401k
• Stock Options