Role OverviewAs a CPU Microarchitecture/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores, based on the revolutionary open-source RISC-V architecture.
What You Will Do
Responsibilities include architecting, designing, and implementing new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel, integrating new design content into SiFive's Chisel/FIRRTL framework, and contributing to improvements to that framework.
Why It Might Be a Fit
The ideal candidate will have a strong background in CPU RTL design, experience with Chisel, and a passion for working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.
Requirements
- BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience
- 7+ years of design experience
- Academic or professional experience with CPU RTL design in one or more of the following areas: instruction fetch, instruction decode, branch prediction, coherent caches, cache prefetching, TLBs
- Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL
- Strong software engineering skills/background, including object-oriented, aspect-oriented, and particularly functional programming, templated metaprogramming, compiler infrastructures, data modeling, and test-driven development
Benefits
- Market-based pay structure
- Variable/incentive compensation
- Equity
- Comprehensive, competitive benefits package
- Healthcare and retirement plans
- Paid time off
- More
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