Senior Technical Lead - Post Silicon Validation

HCL Technologies
Santa Clara, CA
Job Description
Role Overview

Develop and execute tests for collective communication operations on custom networking silicon, validating the ASIC's ability to enable large-scale distributed AI training workloads.

What You Will Do

Develop test suites, write RDMA verbs-level tests, validate multi-node collective communication patterns, and integrate tests into CI/CD pipelines.

Why It Might Be a Fit

Must have deep understanding of RDMA operations, RoCE v2, collective communication operations, and Ethernet/L2 networking. Experience with pre-silicon validation environments, open-source RDMA/networking projects, and build systems at scale is a plus.

Requirements

  • RDMA (Remote Direct Memory Access) — Deep understanding of RDMA operations: READ, WRITE, SEND, RECEIVE; Queue Pairs (QPs), Completion Queues (CQs), Memory Regions (MRs), Protection Domains (PDs)
  • RoCE v2 — Understanding of RDMA over Converged Ethernet protocols, transport-level behavior, and conformance requirements
  • Collective Communication Operations — AllReduce, AllGather, ReduceScatter, AllToAll; ring/tree algorithms; understanding of how collectives map to network traffic patterns
  • Ethernet / L2 Networking — Layer 2 fundamentals, MTU, multiport networking, VLANs
  • PCIe Architecture — PCIe endpoint/switch topology, Gen5/Gen6, BAR regions, MSI-X interrupts, SR-IOV, multi-function devices
  • NCCL / Communication Libraries — Familiarity with NVIDIA Collective Communications Library or equivalent; understanding of how training jobs use collectives over RDMA NICs

Benefits

  • medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance
  • employee assistance program
  • 401(k) retirement plan
  • 10 days of paid time off per year
  • 10 paid holidays per year
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