Senior Test Engineer

Qorvo
San Jose, CA
Job Description
Role Overview

The Senior Test Engineer will build test infrastructure for wafer-level and package-level RF-MEMS testing, develop and maintain automated test programs, and lead validation strategy. They will collaborate cross-functionally with RF design, MEMS design, process engineering, reliability, and product engineering teams. The role requires strong experience with LabVIEW, NI TestStand, and C#, as well as expertise in wafer-level RF/DC testing, probe card design, and qualification.

What You Will Do

The Senior Test Engineer will build test infrastructure, develop and maintain automated test programs, lead validation strategy, debug test programs, and design, qualify, and maintain probe cards. They will also support manufacturing ramp, transitioning test programs and hardware into production environments and improving throughput.

Why It Might Be a Fit

The ideal candidate will have 5+ years of experience in semiconductor test engineering, RF test, MEMS test, or mixed-signal ATE development, and demonstrated ownership of test infrastructure or validation strategy. They will also have strong experience with LabVIEW, NI TestStand, and C#, as well as expertise in wafer-level RF/DC testing, probe card design, and qualification.

Requirements

  • 5+ years of experience in semiconductor test engineering, RF test, MEMS test, or mixed-signal ATE development
  • Strong experience with LabVIEW, NI TestStand, and C#
  • Expertise in wafer-level RF/DC testing, including probe-station workflows, and tester calibration
  • Experience with probe card design, qualification, and maintenance
  • Ability to read and interpret schematics for test boards, probe cards, and driver circuits
  • Hands-on debugging of test programs, hardware bring-up, and instrument communication

Benefits

  • Competitive base salary commensurate with experience
  • Total Rewards package (details available upon request)
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