Staff Implementation Engineer

Requirements

• Full chip and block level constraint development, timing analysis & timing closure
• Develop methodology and flows related to synthesis, timing verification, timing closure and quality checks.
• Work closely with various multi-functional teams to understand and resolve complex timing challenges at block level and chip level.
• Bachelor’s degree with 8+ years of experience, or Master’s degree with 6+ years of experience
• Strong fundamentals in digital design
• Solid understanding of design timing concepts, constraint development and timing analysis
• Hands on experience running STA tools (Tempus/PrimeTime)
• Hands on experience running Synthesis (Genus/DC)
• Hands on experience running LEC (Conformal/Formality)
• Familiarity with DFT
• Proficient in scripting languages (TCL, Python, Perl)
• Strong debug and problem-solving skills
• Ability to communicate across all functional groups
• Self-starter, curious and highly motivated to learn and contribute to team success

Benefits

• Flexible and inclusive work environment
• Remote work option
• Employee Resource Groups
• Hybrid work model